The present invention generally relates to a metal-oxide-semiconductor (MOS) device and, more particularly, to a double diffused drain (DDD) MOS device with a floating poly thereon and a method of fabricating the same.
Serving as elements of the power ICs, the MOS devices have to possess the capability of sustaining high operating voltage. To sustain high operating voltage, however, the distance between the gate and drain of a conventional MOS device generally has to be kept large enough, which may hinder the MOS device from downsizing, as will be discussed below.
FIGS. 1A and 1B are schematic cross-sectional views illustrating a MOS device 1-1 in prior art. Referring to FIG. 1A, the MOS device 1-1 may include a p-type substrate 10, a plurality of first isolation structures 13 on the substrate 10, an n-well region 11 and a p-well region 12 within the substrate 10, a high-voltage “p” minus (HVPM) region 17-1 within the n-well region 11, a pair of p+ regions 18-1 with one in the HVPM region 17-1 and the other one in the n-well region 11, a high-voltage “n” minus (HVNM) region 17-2 within the p-well region 12, and a pair of n+ regions 18-2 with one in the HVNM region 17-2 and the other one in the p-well region 12. Furthermore, the MOS device 1-1 includes a patterned dielectric layer on the substrate 11, wherein the patterned dielectric layer comprises a first portion 14-1 and a second portion 14-2, and a patterned conductive layer on the patterned dielectric layer, wherein the patterned conductive layer comprises a first portion 15-1 and a second portion 15-2. A plurality of second isolation structures 16 may be formed along the sidewalls of the patterned dielectric layer and the patterned conductive layer.
The MOS device 1-1 may serve as an element in power management integrated circuits (PMICs) and operate at a relatively high voltage such as 12 volts (V). In some applications, the distance W0 between the gate, i.e., the first portion 15-1 of the patterned conductive layer and the drain, i.e., the p+ region 18-1 in the NVPM region 17-1 may be 1.2 micrometers (μm) or greater so as to sustain such a high voltage. Moreover, the higher the operating voltage, the greater the distance W0. For example, as the MOS device 1-1 operates at a voltage of 16V, the distance W0 may be increased to 1.5 μm. Furthermore, as the MOS device 1-1 operates at a much higher voltage, for example, 800V, the distance W0 may be increased up to 80 μm.
Referring to FIG. 1B, a MOS device 1-2 may be similar to the MOS device 1-1 described and illustrated with reference to FIG. 1A except that, for example, the MOS device 1-2 includes a pair of HVPM regions 17-1 and 19-1 and a pair of HVNM regions 17-2 and 19-2. The MOS device 1-2 has the same issue as the MOS device 1-1 and similarly may have difficulty in downsizing.
It may therefore be desirable to have a MOS device that is capable of sustaining high operating voltage without significantly increasing the gate-to-drain distance W0.